结合新一代高集成度三维集成电路和新型相变存储技术,以三维相变存储单元阵列的实现为目标,进行了用于存储单元的驱动和开关作用的二极管阵列的制备实验.在借助低温等离子体活化键合技术获得了良好的键合界面之后,利用智能剥离法成功转移了单晶PN结二极管层到含有金属W电极阵列的基片上,并制备了垂直二极管阵列.经过聚焦离子束加工和电镜观察得知基片上小型W电极与转移来的PN结构Si层接触良好,测试得到了标准的二极管特性曲线,开关比达到4个数量级.不过实验制备的二极管漏电流较大,开关比偏低,这些问题还需要在将来实验环境的改进和工艺的优化中得到解决.
参考文献
| [1] | Feng Rao;Zhitang Song;Yuefeng Gong;Liangcai Wu;Bo Liu;Songlin Feng;Bomy Chen .Phase change memory cell using tungsten trioxide bottom heating layer[J].Applied physics letters,2008(22):223507-1-223507-3-0. |
| [2] | 宋志棠,刘波,封松林.纳米相变存储技术研究进展[J].功能材料与器件学报,2008(01):14-18. |
| [3] | Kwang-Jin Lee;Beak-Hyung Cho;Woo-Yeong Cho;Sangbeom Kang;Byung-Gil Choi;Hyung-Rok Oh;Chang-Soo Lee;Hye-Jin Kim;Joon-Min Park;Qi Wang;Mu-Hui Park;Yu-Hwan Ro;Joon-Yong Choi;Ki-Sung Kim;Young-Ran Kim;In-Cheol Shin;Ki-Won Lim;Ho-Keun Cho;Chang-Han Choi;Won-R .A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput[J].IEEE Journal of Solid-State Circuits,2008(1):150-162. |
| [4] | Kim, Y.;Yun, J.-G.;Park, S. H.;Kim, W.;Seo, J. Y.;Kang, M.;Ryoo, K.-C.;Oh, J.-H.;Lee, J.-H.;Shin, H.;Park, B.-G. .Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray[J].IEEE Transactions on Electron Devices,2012(1):35-45. |
| [5] | Ji ZHANG;Yiqing DING;Xiaoyong XUE;Gang JIN;Yuxin WU;Yufeng XIE;Yinyin LIN .A 3D RRAM Using a Stackable Multi-Layer 1TXR Cell[J].IEICE transactions on electronics,2010(12):1692-1699. |
| [6] | Xiaobo Ma;Xiaofeng Du;Weili Liu;Chao Chen;Zhitang Song;Chenglu Lin .Enhanced surface blistering of germanium with B~+/H~+ coimplantation[J].Journal of Vacuum Science & Technology, B. Microelectronics and Nanometer Structures: Processing, Measurement and Phenomena,2009(3):1063-1067. |
上一张
下一张
上一张
下一张
计量
- 下载量()
- 访问量()
文章评分
- 您的评分：
-
10%
-
20%
-
30%
-
40%
-
50%