依据 JEDEC 标准采用板级跌落实验研究晶圆级芯片尺寸封装 Sn?3.0Ag?0.5Cu 焊点的跌落失效模式。发现存在六种失效模式，即发生在印刷电路板(PCB)侧的短 FR-4裂纹和完全 FR-4裂纹，以及发生在芯片侧的再布线层(RDL)与 Cu 凸点化层开裂、RDL 断裂、体钎料裂纹及体钎料与界面金属间化合物(IMC)混合裂纹。对于最外侧的焊点，由于 PCB 变形量较大且 FR-4介质层强度较低，易于形成完全 FR-4裂纹，其可吸收较大的跌落冲击能量，从而避免了其它失效模式的发生。对于内侧的焊点，先形成的短 FR-4裂纹对跌落冲击能量的吸收有限，导致在芯片侧发生失效。
To reveal the drop failure modes of the wafer level chip scale packages (WLCSPs) with Sn?3.0Ag?0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board (PCB) side, split between redistribution layer (RDL) and Cu under bump metallization (UBM), RDL fracture, bulk cracks and partial bulk and intermetallic compound (IMC) cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
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