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采用溶胶-凝胶工艺(Sol-Gel)在Pt/Ti/SiO2/p-Si衬底上成功制备了低漏电流Bi4Ti3O12(BIT)铁电薄膜,对所得样品的漏导行为进行了研究.研究表明,Bi4Ti3O12薄膜的漏电流密度在+3V偏压下低于10-9A/cm2,满足器件应用的要求.在不同场强下薄膜的漏导机制不同,而且正向和负向电场作用下I-V曲线明显不同,正向漏电流明显小于负向漏电流.电压低于2V时,薄膜以欧姆导电机制为主,电压在2~5.4V(加正向电压)或2.2~3.6V(加负向电压)时,BIT薄膜应以Schottky emission导电机制为主;而对于较高的场强下,BIT薄膜以Space-charge limited currents(SCLC)导电机制为主.

参考文献

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