对几种常用的图像缩放算法进行了比较,在权衡了算法复杂度、缩放效果和FPGA逻辑资源等3大因素后,选择了双线性插值算法来实现图像缩放.重点介绍了双线性插值算法和该方法的FPGA硬件实现方法,包括图像数据缓冲单元、插值系数生成单元以及插值计算单元等.应用结果表明,双线性插值算法及其硬件实现模块达到了预期的效果.
Some commonly used image scaling algorithms were introduced, as well as a com-parison among several algorithms. After weighing the algorithm complexity, zoom effects and FPGA logic resources, etc. , the bilinear interpolation algorithm was chosen to achieve image scaling. This work focused on the bilinear interpolation algorithm and the method of FPGA hardware implementation, including image data buffer unit, interpolation coefficient generating unit, as well as the interpolation calculation unit. The realized results show that the bilinear interpolation algorithm and its hardware realizing modules achieve the desired results.
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