A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented.In this paper,a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals.As a result,the linearity of the SAR ADC will increase with high linearity sampled signals.Farther more,a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology.Additionally,the proposed comparator provides a better performance with the decreasing of power supply.Moreover,a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50％ register delay.Lastly,an asynchronous trimming method is provided to make the capacitive-DAC settle up completely instead of using the redundant cycle which would prolong the whole conversion period.This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm2 and consumes 1.8 mW.The SAR ADC achieves SFDR ＞ 68 dB and SNDR ＞ 57 dB,resulting in the FOM of 28 fJ/conversion-step.From the test results,the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.